By their nature, logic circuit designs are timing dependent. Therein, most signals within a logic design must be synchronized with each other. However, there are instances where signals intended to be synchronized are not. For example, between two logic signals, one may be processed through a logic circuit faster than the other, and thereby the signals become non-synchronized. When this occurs, the faster of the two signals is typically time delayed so as to synchronize it with the other signal. One synchronization mechanism for implementing a time delay is known as a time delay buffer.
On a fundamental level, a timing delay buffer can be thought of as adding a predetermined amount of time delay to a circuit. In practice, a time delay buffer is generally inserted into a signal path so as to intercept a signal, add a predetermined amount of time delay to the signal, and then retransmit the time delayed signal onto the signal line. This accomplished, a faster logic signal can be time synchronized with a slower logic signal.
Time delay buffers can be formed from a chain of semiconductor inverters with their inputs and outputs connected in series. FIG. 1 illustrates an example of such a timing delay buffer. A set of inverters 120 are connected in series, such that an input signal at node 105 will appear as a time delayed signal at node 110. In this configuration of a timing delay buffer, the sum total of each inverter's delay time determines the total delay time of the series of inverters.
A common problem encountered in circuit 100 and circuits of similar design, is that an inverter's delay time (i.e. the propagation time) will vary due to fabrication process variations, and due to variations in operating conditions of the die. Therefore, the range of the total delay time, of the series of inverters of FIG. 1, can vary widely as fabrication and operating conditions vary. The greater the number of inverters in a series, the greater the possible variations in total delay time.
Note that performance variations can be due to, for example, (1) semiconductor fabrication process variations, and (2) operating condition variations. Fabrication process variations include variations in, for example, oxide thickness, transistor geometries, internal polysilicon capacitance, n-channel or p-channel capacitance, metal line resistance and capacitance, and the like. Operating condition variations include variations in, for example, power supply voltages, and variations in temperature of the die or circuit during operation. Collectively, variations due to process, voltage and temperature are known as PVT variations, while variation due to voltage and temperature are known as VT variations.
FIG. 2 illustrates another typical time delay buffer circuit 200, that includes a driver 215, capacitive load 220, and load 275. Note that the driven signal from any semiconductor drive circuit, including driver 215 of FIG. 2, will have some inherent slew rate (change in voltage per unit time) due to the nature of the fabrication process and the materials used in the process.
To create a time delayed signal, circuit 200 adds a capacitive load 220 to the output of driver 215 at node 217. Capacitive load 220 decreases the inherent slew rate (and increases the rise time) of a signal on node 217. In turn, the decreased slew rate of the signal at node 217, adds a time delay to the signal at node 210. For example, load 275 has a fixed threshold voltage for a logic "0" or "1" at node 217 for any signal appearing on node 217. Capacitance 220 elongates the rise or fall times of a signal at node 217 such that load 275 will recognize a logic transition at a later point in time then if capacitive load 220 were not present. Therefore, an input signal at node 205 will appear as a time delayed signal at node 210, where the value of the capacitance of capacitive load 220, determines the amount of time delay.
A common problem in circuit 200, and in similar circuits, is that the slew rate of any inverter will vary over PVT variations. Therefore, when delay buffer driver 215 is affected by PVT variations, resulting in an other than nominal slew rate signal from driver 215, the time delay of the circuit is disturbed from a desired nominal time delay. Additionally, circuit 200 generally does not correct this problem because capacitive load 220 (for example, a pMOS and an nMOS capacitor) will also vary in an uncontrolled manner due to PVT variations.
Attempts have been made to compensate circuit 200, and similar circuits, for PVT variations. For example, large channel transistors have been used in an attempt to decrease process variation effects. However, use of large channel transistors only passively compensates for PVT variations, and they also have the disadvantage of using large amounts of die area.